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**Review of a Complete Summator Performed with OR Exclusive Doors and NAND : **

**4. - THIRD EXPERIENCE : EXAMINING A COMPLETE SOMMATOR**

A full summator takes into account the hold of the previous summing circuit and of course generates the hold for the next circuit.

It therefore has **three inputs** and **two outputs** as shown in Figure 7-a.

The table of the retaining addition in Figure 7-b corresponds in practice to that obtained when three bit numbers of one bit are added between them, one of which is the retention of the previous partial sum.

For example, consider the following three sums **:**

**4. 1. - REALIZATION OF THE CIRCUIT**

**a)** Leave the integrated circuits **MM 74C86** and **MM 74C08** on the matrix and remove all the links.

**b)** Insert the integrated circuit **MM 74C32** on the matrix in the position shown in Figure 8-a and make the corresponding connections.

The circuit diagram is given in Figure 8-b.

**4. 2. - OPERATING
TEST**

**a)** Turn on the Digilab.

**b)** Try the different combinations of the three switches **SW0, SW1** and **SW2** and check each time that the circuit performs the sum function according to the table of figure 7-b..

For example, with **SW0** on position **0, SW1** on **1** and **SW2** on **1, L0** should be off and **L1** on. This situation corresponds to **: 0 + 1 + 1 = 10.**

**c)** With the experiment complete, turn off the Digilab. In summary, with the circuit under examination, it is possible to add three **1 bit** numbers. When the sum and the hold are equal to **1,** we obtain the maximum result **11** equivalent to the decimal number **3.**

In the next experiments, you will see how with a single complete summator associated with other circuits, you can add numbers as big as you want.

**
5. - FOURTH EXPERIENCE : EXAMINATION OF A COMPLETE
SUMMIT REALIZED WITH DOORS OR EXCLUSIVE AND NAND**

You will now experience a circuit that performs the same functions as the circuit of the third experiment but uses one less integrated circuit.

The full summoner is called in English **full adder.**

**5. 1. - REALIZATION OF THE CIRCUIT**

**a)** Remove from the matrix the links and integrated circuits related to the previous experiment with the exception of the **MM 74C86.**

**b)** Insert the integrated circuit **MM 74C00** (**Quad NAND**) on the matrix and make the connections shown in Figure 9-a.

The electrical diagram of the realized circuit is given in Figure 9-b.

**5. 2. - OPERATING TEST**

**a)** Turn on the Digilab.

**b)** Try the different combinations of the three switches **SW0, SW1** and **SW2** and check each time that the circuit works as a complete summator.

**c)** With the tests completed, turn off the Digilab.

If you compare the circuit experienced here with that of the previous experiment, you notice that this second circuit, while being different and using a smaller number of integrated circuits, performs the same function.

When it is necessary to realize a logical function, it is important to minimize the number of integrated circuits even if this entails the necessity of using more complex integrated circuits.

In the second part of this practice, you will have the opportunity to realize this, using **the multiplexers.**

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